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[TERASIC] ALTERA Cyclone III DE0
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 [TERASIC] ALTERA Cyclone III DE0
 
 Altera Cyclone III Development and Education board
 
 
ÆǸŰ¡°Ý 231,000 ¿ø(VATÆ÷ÇÔ)
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Overview

The DE0 Development and Education board is designed in a compact size with all the essential tools for novice users to gain knowledge in areas of digital logic, computer organization and FPGAs. It is equipped with Altera Cyclone III 3C16 FPGA device, which offers 15,408 LEs. The board provides 346 user I/O pins, and is loaded with a rich set of features that makes it suitable to be used for advanced university and college courses, as well as the development of sophisticated digital systems. The DE0 combines the Altera low-power, low-cost, and high performance Cyclone III FPGA to control the various features of the DE0 Board. The DE0 Development Board includes software, reference designs, and accessories required to ensure the user simple access in evaluating their DE0 Board.

 

Specification

  • FPGA
    • Cyclone III 3C16 FPGA
      • 15,408 LEs
      • 56 M9K Embedded Memory Blocks
      • 504K total RAM bits
      • 56 embedded multipliers
      • 4 PLLs
      • 346 user I/O pins
      • FineLine BGA 484-pin package
  • Memory
    • SDRAM
      • One 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip
    • Flash memory
      • 4-Mbyte NOR Flash memory
      • Support Byte (8-bits)/Word (16-bits) mode
    • SD card socket
      • Provides both SPI and SD 1-bit mode SD Card access
  • Interface
    • Built-in USB Blaster circuit
      • On-board USB Blaster for programming
      • Using the Altera EPM240 CPLD
    • Altera Serial Configuration device
      • Altera EPCS4 serial EEPROM chip
    • Pushbutton switches
      • 3 pushbutton switches
    • Slide switches
      • 10 Slide switches
    • General User Interfaces
      • 10 Green color LEDs
      • 4 seven-segment displays
      • 16x2 LCD Interface (Not include LCD module)
    • Clock inputs
      • 50-MHz oscillator
    • VGA output
      • Uses a 4-bit resistor-network DAC
      • With 15-pin high-density D-sub connector
      • Supports up to 1280x1024 at 60-Hz refresh rate
    • Serial ports
      • One RS-232 port (Without DB-9 serial connector)
      • One PS/2 port (Can be used through a PS/2 Y Cable to allow you to connect a keyboard and mouse to one port)
    • Two 40-pin expansion headers
      • 72 Cyclone III I/O pins, as well as 8 power and ground lines, are brought out to two 40-pin expansion connectors
      • 40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives

     

    Layout


    Resoures

    DE0 Debounce Project contains a new DE0 top Quartus project with debounce IP, as well as a DE0 debounce
    demonstration. For more information on the project and demo, please read the "readme.txt" file included.

     

    Documents

    TitleVersionSize(KB)Date AddedDownload
    DE0 User Manual - 5767 2011-03-22
    DE0 Debounce Project - 97 2010-07-30

    CD-ROM

    TitleVersionSize(KB)Date AddedDownload
    DE0 Control Panel V1.0.3 -   2011-07-08
    DE0 CD-ROM & Control Panel -   2010-05-24

    Please note that all the source codes are provided "as is". For further support or modification, please contact Terasic Support and your request will be transferred to Terasic Design Service.
    More resources about IP and Dev. Kit are available on Altera User Forums.

    DE0 Reference Designs

    • SD Card reader
    • VGA Color Pattern

    DE0 Control Panel

    • DE0 Control Panel allows users to access various components on the board from a host computer.



    Kit Contens

    The DE0 package includes:

    • Altera DE0 Board
    • USB Cable
    • DE0 CD including£º
      • Altera's Quartus? II Subscription & Web Edition and the Nios? II Embedded Design Suit Evaluation Edition software
      • DE0 User Manual, Quick Start Guide
    • DE0 Acrylic
    • Adapter DC 7.5V/0.8A (US wall plug)



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